A Low Redundancy Matrix Code Technique for Resistant to Single-Particle Flip-Flops
Di Zheng, Qing-Quan Liu, Ronghua Shi, Yu Wang, Zhenpeng Jiang · 2024
A low redundancy matrix code technique is proposed to address the problem that Static Random Memories (SRAM) are prone to single-particle Multiple Bit Upsets (MBU) within a single memory word. The design of the low-redundancy matrix code is based on the idea of using low-complexity multi-bit error detection methods for each row and column of information bits, respectively. It is verified that the proposed low redundancy matrix code requires fewer redundant memory cells to correct all soft errors up to four consecutive and non-consecutive bits, which greatly improves the reliability of the memory. The encoder and decoder of the low-redundancy matrix code are implemented in Vivado integrated environment using Verilog hardware description language, and their functions are simulated and verified and performance analyzed. Compared with currently known matrix codes, the proposed low-redundancy matrix code technique can reduce the redundancy overhead of parity bits by up to 30% and achieve a code rate of 0.35.