Empowering Ultra-Low Power with RISC-V ISA Extension Using Reversible Logic Gates for IOT Devices
Bikram Kumar, K Soni, Ashok Sangala, Chelimala Anjani, U Bhagyalakshmi · 2024
An open-source RISC-V instruction-set augmentation (RV32IM) is introduced in this study for use in software-defined Wi-Fi Internet of Things (IoT) transceiver devices with very low power consumption. The purpose of the updated instructions is to address a widespread need for complicated math in quadrature modulations using $8 / 16 / 32$ bits of numerical data. For the most part, the suggested extension’s energy cost is near to nothing, and it uses only two main op-codes. The two novel architectural models, the instruction exact (IA) and the process accurate (CA), are used to evaluate six IoT test seats, such as FSK demodulating and LoRa preamble detection. Simulation findings reveal a large variation in cycle count improvements, ranging from $19 \%$ through $68 \%$. In post-synthesis simulations, the 22 nm FD-SOI technology outperforms a baseline RV32IM design with an electricity overhead of less than $1 \%$ and an area overhead of $28 \%$. According to the power calculations, for $\mathrm{BW}=500 \mathrm{kHz}$ with $\mathrm{SF}=11,380 \mu \mathrm{~W}$ is used for Bluetooth LE demodulation by peak electrical power, and $225 \mu \mathrm{~W}$ is used for LoRa preamble detection.