Efficiency Unleashed Montgomery Modular Multiplier
K R Kavitha, S Vijayalakshmi, B. Murali Babu, B K Kirthivasan, R Negaasri · 2024
This, in fact is the knowledge generation hypothesis, where the imposition of knowledge barrier will be broken upon the launching of a novel high throughput barrier resilient Montgomery multiplier, which takes full advantage of optimal Barrett reduction which is actually in quest of further improvement of modular multiplication for applications on cryptographic systems as well as digital signal processors. Because Montgomery multiplication is intrinsically parallel and the reduction is included within it, such an architecture provides high throughput with very low latency. While such sophisticated design is being embedded within the optimization of the hardware implementations, such optimization will be based on a practical orientation aimed at maximizing parallel processing, pipelining, and resource sharing, while minimizing the critical path delay. In addition to that, it takes care of the smart problem of the input and output data formats for ease in its integration into the existing system and protocols. However, the simulation and synthesis measure and quantify the performance, area, and power consumption extension of this work in comparison with the classical methods of design. This work, in the end, would allow accelerating important cryptographic operations within any kind of resource-centric environment, providing improvements toward efficiency and better security in many cryptographic techniques and their real-world applications.