Serial Peripheral Interface with SOC Using Universal Verification Methodology
N. Bhuneswary, K. Kiran Kumar Reddy, M. Chandrashekar Reddy, Kothamasu Venkata Sivanaga Sai, K. Satyanarayana · 2024
The Scalability and complexity nature of the integrated circuit design makes the verification process more complicated and time-consuming. Therefore, there is a strong need for verification architecture with increased reusability and easy accessibility in today's modern day SOC. The UVM methodology -based verification architecture with reusable components is one of the widely accepted test bench architecture for carrying out such functional verification.. In addition, by using a result comparison function and limiting the frequency of accidental excitation it is possible to fully verify the SPI function at minimum percentage coverage rate. We can increase the efficiency of code coverage and functional coverage through the SPI interface. Full verification of the SPI function, with a coverage rate of 95.64 %, has been achieved through the use of a constrained random excitation and an automatic result comparison function. Lastly, a successful migration to the SOC verification environment has been achieved for the SPI module's validation environment.