Efficient Hardware Accelerator Design for AES Encryption Using High-Level Synthesis Techniques
B.S.S. Tejesh, M. Ramakrishnan · 2024
In this work, we present the design and implementation of a hardware accelerator for AES encryption and decryption using AMD Vitis HLS and Xilinx Vivado. The primary objective of this work is to maximize the throughput, with optimizations focusing on resource utilization and power consumption. We detail the design methodology, provide an in-depth analysis of resource utilization, and compare our results with existing AES hardware accelerators. The hardware accelerator has been deployed on a PYNQ-Z2 FPGA board, achieving a throughput of 20.8 Gbps at 650 MHz, Total power consumption of 1.418W. The results show significant performance improvements, demonstrating the viability of high-level synthesis (HLS) for cryptographic applications on FPGAs.