Accelerating PageRank Algorithmic Tasks with a new Programmable Hardware Architecture
Md Rownak Hossain Chowdhury, Mostafizur Rahman · 2024
Addressing the growing demands of artificial intelligence (AI) and data analytics requires new computing approaches. In this paper, we propose a reconfigurable hardware accelerator designed specifically for AI and data-intensive applications. Our architecture features a messaging-based intelligent computing scheme that enables dynamic programming at runtime using a minimal instruction set. To assess our hardware's effectiveness, we conducted a case study using TSMC 28nm technology node. The simulation-based study benchmarks our hardware against the Tensor Processing Unit (TPU) and involves analyzing a protein network using the computationally demanding PageRank algorithm. The results indicate that our hardware can analyze a 5,000-node protein network in just 213.6 milliseconds over 100 iterations. Moreover, our design outperforms systolic array based TPU demonstrating an 11% reduction in latency for matrix vector multiplication. These outcomes signify the potential of our design to achieve cutting-edge performance in next-generation AI applications.