Language semantics to support secure computation and communication in embedded systems via hardware monitors
Garett Cunningham, Siqin Liu, Harsha Chenji, David W. Juedes, Avinash Karanth · Integration · 2025
As embedded systems with manycores and Network-on-Chips (NoCs) become ubiquitous, emerging hardware and software vulnerabilities have made it challenging to ensure system integrity especially when third-party intellectual property (IP) is used for rapid prototyping. Prior works have evaluated hardware monitors for ensuring correctness of the system by threat assessment and effective mitigation. However, none have evaluated models that combine both computation (processor pipeline) and communication (NoC) vulnerabilities simultaneously. In this paper, we propose a high-level policy language called d-GUARD that is used to define runtime security policies that can be compiled into hardware monitors. The advantage of this new language is the ability to dynamically change policies based on program’s runtime behavior. To translate high-level policies into low-level hardware monitors, we describe a compiler for d-GUARD that synthesizes policies into Verilog modules. Instead of simply evaluating the design of secure policies for processor pipelines, we extend to secure NoC microarchitectures, including policies for links and routers, as well as policies to prevent Denial-of-Service (DoS) attacks. To mitigate attacks against secure microarchitectures, we also propose fault-tolerant routing approaches to avoid rogue routers when the number of policy violations exceeds a certain threshold. Our secure policies for processor pipelines and NoC microarchitectures consume marginal area and power overhead when compared to baseline making it well suited for low-cost embedded systems. • A high-level security policy language called D-GUARD, which is expressive, modular and compatible with power-efficient hardware is proposed. • The proposed dynamic policies implemented at various levels of the embedded enable low-cost monitors that can be modified based on application demands. • The runtime costs of the processor pipeline using OptimSoC, an open-source implementation of OpenRISC1000 architecture where processor policies are evaluated, which showed less than 1% overhead in power and area when implemented in 14 nm and 45 nm technologies and no performance overhead when implemented on BEEBS benchmark suite.