Up to 60% More Linear Area Efficient Asymmetric 6T (6TA) SRAM Cell for In-Memory Compute
Ajay Shroti, Anuj Grover · 2024
In-memory compute (IMC) based approaches have lower power consumption and improve performance by avoiding the Von-Neumann bottleneck in advanced processors. In this work, we propose an asymmetrical 6TA SRAM cell for IMC operation and benchmark it with 6T SWL (split wordline), 8T, 9T1C, and C3SRAM cells. Our analysis shows that the proposed 6TA cell is about 60% more linear, provide higher throughput due to 1.15X lesser variability, and has the same area as the 6T SWL cell in 130nm CMOS technology.