Efficient Hardware Architectures for Log-Likelihood Ratio Estimation in Correlated Noise Environments
Emmanouil Kavvousanos, Vassilis Paliouras · 2024
Correlated noise can impair the performance of a digital receiver and pose challenges for the error-correction decoder. In this paper, noise correlation is utilized constructively in the derivation of log-likelihood ratios (LLRs), i.e., the typical input form of soft error-correction decoders. The derived LLRs account for noise correlation, demonstrating significant performance improvements by a subsequent error decoder. The proposed approach stems from simplifications of the maximum-likelihood detector. A complexity analysis reveals that the increase in underlying hardware cost is reasonable, considering potential simplification in the error decoder, as well as in the simplification of any noise-whitening construct. Extensive trade-offs are possible, while approximations and data reuse is shown here to reduce the cost by a factor of ×3, while resulting in substantial code gains over conventional approaches. Furthermore, the derived hardware architectures can be efficiently pipelined and unrolled.