RISC-V Core with AES-256 Accelerator
Otto Simola, Aleksi Korsman, Verneri Hirvonen, Antti Tarkka, Julius Helander, Kimmo U. Jarvinen, Marko Kosunen, Jussi Ryynänen · 2024
This paper presents a RISC-V core integrated with a cryptographic accelerator for 256-bit Advanced Encryption Standard (AES-256). It supports several block cipher modes and has been integrated as an extension to a 5-stage RV32IMFC RISC-V core implemented in 22 nm FD-SOI. For performance comparison, the hardware accelerator was verified with an extensive verification environment involving simulations and testing with Field Programmable Gate Array (FPGA) and Application-Specific Integrated Circuit (ASIC) implementations against a C-program solution implemented with the openSSL library, running on the implemented RISC-V core. The accelerator achieves 82–84% faster AES cipher operation compared to the software solution.