GNN-Based Timing Prediction in Prerouting Stage With Multitask Learning Strategy
Zihao Lin, Haisen Zhang, Peng Gao, Fei Yu, Tingting Wu, Xiaoming Xiong, Shuting Cai · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2025
Static timing analysis tools are commonly used to evaluate timing performance and guide optimization during placement stage. However, traditional timing analysis struggles to fast and accurately evaluate timing violation due to absence of detailed routing information necessary for RC parasitic parameter extraction. Therefore, a timing analyzer based on graph neural network is proposed in this article. Compared to previous works, a novel representation of circuit delay model is proposed in this article, employing timing arcs and virtual pins to predict net delay and arrival time (AT) in the prerouting phase. Additionally, to our knowledge, this is the first attempt to improve the quality of timing analyzer through a strategy of multitask learning, with the proposed enhanced dynamic weight average method. The experimental results demonstrate that our model excels in predicting net delay and AT, with average correlations of 0.9540 and 0.9058, respectively, on the testing set. In comparison to the previous state-of-the-art methods, our approach maintains accuracy in net delay prediction while enhancing the overall$R^{2}$score for AT prediction by 0.0271. Additionally, our method reduces inference time by 25.8%.