VLSI Technology used in Floating Point Multipliers Used in Vedic Mathematics Calculation
Towheed Sultana, Md. Salauddin, G. Nithya, Shashi Kant Dargar, Amit Gupta · 2024
All digital systems' fundamental components are multipliers. There is a rising need for low-delay multipliers in a variety of applications involving digital signal processing. These applications require minimal latency and fast processing. The necessity for accurate and quick floating-point arithmetic has grown along with the demand for these applications. In this study, a floating-point multiplier is constructed using the Urdhva-Tiryakbhyam (UT) sutra, a method of Vedic mathematics. Our goal is to demonstrate that Vedic multipliers outperform current multiplier technology. Cross-multiplication is the first phase of the Urdhva-Tiryakbhyam method, which is followed by addition.The Vedic Multiplier is next examined, and its results are contrasted with those of an array multiplier. The 90nm standard cell library for Cadence EDA Tool was used to build the designs. The Virtuoso tools are used to perform the benchmarking and comparisons. A traditional multiplier is also created, and its performance is compared to that of the Vedic multiplier using a variety of adders. The multipliers are contrasted in terms of power and latency.