Performance Enhancement of Network-on-Chip Architecture using Machine Learning Techniques
Ramapati Patra, Hemanta Kumar Mondal · 2024
A scalable and promising interconnect solution for System-on-Chip (SoC) designs is Network-on-Chip (NoC), intended for high-performance computing platforms. The crucial parameters, including throughput, latency, and total energy, directly affect NoCs’ overall performance. Nevertheless, a cycle-accurate simulator requires much execution time as the system size increases. To predict crucial parameters for network-on-chip designs, this work presents a machine-learning approach that uses several regression models. The proposed work explores Linear regression (LR), Support vector regression (SVR), Decision tree regression (DTR), K-nearest neighbour (KNN), Random forest (RF), and Polynomial regression (PR) models to predict various NoC performance metrics. The obtained results are compared with the cycle-accurate simulator for NoCs. The experimental results showed an R2 score of 0.9997, MAPE and RMSE of 0.0058 and 1.48 × 10−5respectively. Moreover, the proposed regression model achieves a maximum speedup of approximately 6257.1X compared to a cycle-accurate simulator. This work outperforms existing works regarding R2 score, MAPE, RMSE, and speedup.