Low Latency Majority Logic Based Multiplier
Jandhyala B V Subrahmanya Praneeth, Sangeetha Kamatchi · 2024
Approximate Computing (AC) presents a compelling approach to reducing energy consumption and footprint by relaxing the requirement for absolute precision. ML-based arithmetic circuits, like multi-bit adders and multipliers, enhance computing accuracy by reducing the propagation of imprecise outputs. This paper introduces a novel multiplier design incorporating a unique Partial Product Reduction (PPR) circuitry derived from the parallel approximation 6:3 compressor, efficiently realized through the application of a novel Wallace tree algorithm. Such approximate adders and multipliers find particular utility in tasks like image processing and machine learning, where speed often outweighs the need for perfect precision. Notably, significant reductions in power and space are achieved without compromising quality, facilitated by the introduction of an approximate 6:3 compressor and a specialized PPR circuit for compression in the multiplier. Furthermore, two distinct multipliers are proposed, each resulting in varied improvements in parameters such as MAE, area, power, and delay. For Design 1, power and delay decrease by 14% and 7%, respectively, while Design 2 exhibits a 16% reduction in MAE and a 2% decrease in delay when compared to an 8x8 existing approximate multiplier.