A Vertical Power Delivery Architecture for High-Performance Computing
Cai Kong, Weiwei Huan, Jian Wang, Dali Li, Hui Sun, Xuehong Zhang, Fenghua Ye, Kaizhi Lin · IEEE Transactions on Power Electronics · 2025
Power delivery is becoming especially critical for high-performance computing system. This article realizes a novel vertical power delivery (VPD) architecture with high delivery efficiency and system computing performance. A 12–1.83 V voltage regulator (VR) board is built via blind/buried via process. Based on compatible design of VR board and mainboard, this VR board has been directly assembled with a server mainboard to form a computing system. Static output and transient response tests indicate superior stability of VPD prototype. Peak and full load efficiencies of prototype are confirmed to be 93.0% and 91.5%, respectively, better than lateral power delivery (LPD) and previous reports. This VPD design also enables direct power supply to central processing unit. Therefore, system computing performances have been further investigated to evaluate application of built VPD in real server environment, and benchmark score of VPD system is acquired to be 15 538, higher than LPD server (14 599). The superior performances can be attributed to reduced power distribution network resistance, revealed by path resistance (Rpath) simulation. At last, we have extended the manufacture process of VR board into mainboard, facilitating direct assembly of power converter on back side of server mainboard. The built VPD realizes scalable efficiencies.