Bayesian Learning-Enhanced Embedded Memory Design With Automated Circuit Variant Generation
Dong-Ho Kim, Junseo Lee, Seokhun Kim, Jihwan Park, Sangheon Lee, Hanwool Jeong · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2025
This article proposes a Bayesian learning driven automated embedded memory design methodology that aims to minimize leakage current, minimize power, and maximize performance while meeting predefined constraints. To achieve this objective effectively, we present an automatic tool that leverages a reference initial circuit design to generate a diverse set of schematic and layout options for logic-equivalent circuit variants and various transistor threshold voltage (Vth) modifications, while ensuring compliance with design rules. Subsequently, leveraging the range of circuit options generated, Bayesian optimization is employed not only to identify optimal circuit parameters but also to select the most appropriate circuit topology and individual transistor$V_{th}$to attain the desired design objectives. TSMC 28 nm process simulation results demonstrate the proposed methodology reducing power by 26.28%–46.44%,$T_{\mathrm { access}}$by 25.60%–42.29%, and leakage current by 22.73%–50.11% compared to the compiler-generated design, with a runtime of 10–40 h.