Dynamic capacity management circuits for memory subsystems
Leran Wang, Qingxin Li, Ying Gao, Jinghao Zhu, Wancai Xu · 2024
In order to cope with the high bandwidth and large capacity requirements of memory in computing systems, this paper proposes a hardware-based dynamic capacity management circuit for memory subsystems. In this paper, we design a hardware-based lightweight dynamic capacity management circuit for the memory subsystem that supports dynamic allocation of memory capacity for multiple hosts according to their workloads, thereby achieving higher memory utilisation. A binary tree is employed to map the memory resources of a single memory device, designated as the local allocator, which is regarded as a logical sub-tree. Subsequently, a further binary tree is constructed to represent the entire memory subsystem, utilising these mapped logical sub-trees, designated as the global allocator. Additionally, a test platform based on the xcvu3p FPGA was constructed. The results of the experiments demonstrated that following the implementation of dynamic capacity management, the memory utilisation increased by up to 17.27%, while the task execution time was reduced by up to 10.79%.