ARCHITECTURAL PATTERNS IN MOBILE CPUS FOR BALANCING POWER, PERFORMANCE, AND AREA (PPA)
Vinay Panchal · INTERNATIONAL JOURNAL OF ELECTRICAL ENGINEERING & TECHNOLOGY · 2025
The mobile CPU architectures represent the cutting-edge of contemporary microprocessors because of power, energy density, and size requirements.Almost like a rule of thumb, that is known as Power, Performance, and Area (PPA), which are fundamental axioms for designing CPUs for powering mobile devices with a limited battery, compact thermals, and formal constraints.To meet these challenges, architects have used unique design techniques, including heterogeneous multi-core processors, dynamic voltage and frequency scaling (DVFS), and advanced nodes, including 5nm and 3nm nodes.Efficiency improvement is a fine balance; thus, these innovations intend to hit high performers with high-intensity chores while minimum usage is low intentions or standby mode.This paper aims to survey various existing architecture patterns for mobile CPUs in light of power consumption, performance, and chip size considerations.The paper focuses on the approaches to measuring PPA, including the provision of benchmark tests and simulations along with PPA analysis in case studies with real-world applications.Thus, by describing the continued development of the Big.LITTLE architecture and reviewing current innovations such as machine learning-based workload control for mobile CPU design, this paper helps identify development trends.