A Unified Verification Scheme for the Acceleration of RISC-V Processor Design
Zixiang Chen, Jiyuan Bai, Yueru Yu, Gengsheng Chen, Xiaofang Zhou · 2024
This paper presents a unified verification scheme for design and verification of large-scale complex digital systems. The new scheme integrates the software simulation environment and the hardware accelerating resources to undertake a unified and automated verification of large-scale digital circuit systems, encompassing test generation, result comparison, and coverage analysis. The non-synthesizable UVM test bench is coupled with the hardware emulator to constitute a generalizable and flexible verification platform. By mapping RTL code to the emulator, the whole simulation process receives a significant acceleration. Besides, a thorough error analysis and coverage assessments validate the effectiveness of the scheme, providing a substantial feedback for designer's successive optimization. We apply this scheme to the verification task of a RISC-V processor design, achieving an up to 5.69x speedup and a comprehensive coverage rate of 93.80%, 18.92% increase over the conventional methods.