A Low Latency and High Throughout Hardware Design of Random Matrix Number Generator for FrodoKEM
Shengfei Gu, Jiahao Lu, Tianze Huang, Jiaming Zhang, Kai Li, Cheng Wu, Mingbo Wang, Xianqi Mei, Ang Hu, Dongsheng Liu · 2024
FrodoKEM is a lattice-based key encapsulation mechanism, based upon the hardness of the Learning With Errors (LWE) problem. It takes great advantage in security by avoiding specific structures within lattices and is under consideration for standardization by International Organization for Standardization (ISO). In this paper, we propose a low latency and high throughout random matrix number generator for FrodoKEM. A pipelined and FrodoKEM-specified Secure Hash Algorithm 3 (SHA-3) structure is designed to reach high throughout and cost relatively little resource. This paper also designs a multi-data-flow fast sampler to save the cycle consumption of the sampling process. The design is implemented on XILINX Zynq UltraScale+ MPSoCs hardware platform. It reaches a max frequency of 400MHz and makes an improvement of 120× on the cycle number when comparing with the HW/SW codesign for FrodoKEM which still runs software and only operates basic operations in hardware.