RISC-V Domain-Specific Processor for Accelerating SPHINCS+ on Multi-Core Architecture
Shengnan Zhang, Yifan Zhao, Xinglong Yu, Jun Shu Han · 2024
SPHINCS+ is a hash-based signature scheme selected for post-quantum cryptography(PQC) standardization announced by the U.S. National Institute of Standards and Technology (NIST) in 2022. However, its slow computation time hinders its practical application, making it crucial to enhance its speed. The computations of SPHINCS+ require the use of tweakable hash functions, which can be selected from various hash operators. Among them, SHA-3 is chosen as a widely recognized and standardized hash function by NIST. This work proposes a coprocessor that includes a SHA-3 accelerator and its peripheral structure. Based on the RISC-V instruction set extension, we construct seven custom instructions for this coprocessor, achieving software-hardware co-acceleration. At the same time, the parallelizability of the FORS and WOTS+ within the SPHINCS+ is analyzed. We develop thread-level parallelism inherent in SPHINCS+ through multi-core programming, thereby achieving performance improvement. Finally, synthesis is conducted using the TSMC 28-nm CMOS technology at 800MHz. Compared to the benchmark results of the ARM Cortex-M4, the single-core acceleration for an overall speedup of SPHINCS+ reaches 23.1×, and the multi-core acceleration achieves an additional speedup of 3.4× for the verification process compared to the single-core.