A Consistency Testing Method for Revealing RISC-V Processor's Undocumented Instructions
Wen Wang, Peng Liu · 2024
The open and flexible nature of the RISC-V instruction set architecture (ISA), while beneficial for innovation, presents challenges in consistency testing for undocumented instructions. These undocumented instructions are not specified in the processor's publicly available documentation but can be executed in hardware, leading to unpredictable behaviors and potential security vulnerabilities. To attack this problem, we propose a consistency testing method to uncover undocumented instructions in RISC-V ISA. This method systematically generates and tests instructions on the fly, ensuring a comprehensive coverage of the instruction set architecture design space. The effectiveness of the consistency our testing method is justified through a case study involving the Veer EH2 processor core. Our experimental results indicate that this method can identify previously unknown instruction bugs, and it performs fastter in testing undefined instruction set encoding compared to the RISC-V DV tool.