Analysis of integer-N phase-locked-loop architecture
Ziyu Chenguo, Zichen Ou, Xinyu Tao · IET conference proceedings. · 2025
Phase-Locked Loops have a wide range of applications as frequency synthesizers. An analysis of Integer-N Phase-Locked-Loop (PLL) is presented in this article. The performance of a phase-locked loop is determined by a number of factors. It is shown whether good locking time performance can be provided by changing the loop bandwidth of the PLL system. The loop filter can be designed to accelerate the lock time because it controls the poles and zeros of the system. The PLL system is a typical Charge-Pump PLL which uses a Ring Voltage-Controlled Oscillator (Ring-VCO) to optimize the area as much as possible and to reduce power consumption. The phase noise of the Ring-VCO at 1MHz is -96.14dBc and the system can deliver a stable output frequency of 1.6GHz with a 100MHz reference clock. The Multi-Modulus Divider (MMD) used can provide divider ratios from 16 to 31. Simulation is done by TSMC 40nm process.