Scalable and Low-Cost NTT Architecture With Conflict-Free Memory Access Scheme
Zhenyang Wu, Ruichen Kan, Jianbo Guo, Hao Xiao · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2025
This brief proposes a scalable multistage and multipath architecture for variable number-theoretic transform (NTT). The proposed architecture adopts multiple parallel paths, each of which uses cascaded radix-2 butterfly units (BFUs). The radix-2 scheme simplifies the control logic and the cascaded BFU structure reduces the amount of RAM banks and the frequency of memory accesses. Moreover, a conflict-free and hardware-friendly in-place memory mapping scheme is proposed to ease the adaption to multiple paths, letting it be scalable for various throughputs. Compared with state-of-the-art works, the proposed architecture uses fewer resources and has better area-time product performance without penalty in throughput.