Design of PUF circuits based on parallel delay arbitration
Xiaolong Yu, Pengjun Wang, Gang Li, Dong Lu · IEICE Electronics Express · 2025
Physical Unclonable Functions (PUFs) represent a promising hardware security technology, particularly under resource-constrained conditions. However, conventional Arbiter PUFs (APUFs) are highly vulnerable to machine learning (ML) attacks. To address this limitation, this paper proposes an innovative PUF circuit design scheme leveraging parallel delay arbitration. The approach involves constructing a two-tiered APUF architecture, where the delay differences of individual path segments are extracted for arbitration. The final PUF response is obtained by XORing the arbitration results, thereby enhancing the linear complexity between the circuit's challenges and responses. This significantly improves the PUF's resistance to ML-based attacks. Experimental results demonstrate that even with a training set comprising 106 challenge-response pairs and employing various ML models for attacks, the prediction accuracy remains substantially lower than that of a 3XOR-PUF with comparable hardware resource utilization. Moreover, the proposed PUF circuit exhibits excellent performance across other critical metrics, achieving a stability of 98.03%, while maintaining nearly 50% randomness and uniqueness.