Systolic Array-Based Accelerator Architecture Combining Iterative Variable-Width Approximate Multipliers
Po-Ying Feng, S.Y. Lee, Yong-Chi Chang, Hsuan-Yu Chiang, Shu-Yen Lin · 2024
In recent years, the iterative approximate multiplier was proposed to replace the exact multiplier in CNN applications. The goal of the iterative approximate multiplier is to reduce the area overhead and power consumption with the acceptable error loss. In this work, Variable-Width Approximate Multiplier (VWAM) is proposed to support the positive and negative inputs of the approximate multiplication with the reduction of the area and power. VWAM is also implemented by the cell-based design with TSMC 90-nm CMOS process. Compared to the related work, 30.55% chip area and 9.84% power consumption are reduced without influencing the accuracy.