Optimizing Multiplier Performance Through Verilog Hardware Description Language Design
Wai Leong Pang, Tania Khatun, Swee King Phang, Ajay Singh, Angie See Tien Ng, Kah‐Yoong Chan · 2024
The Arithmetic Logic Unit (ALU) constitutes a critical component within a computer's Central Processing Unit, responsible for executing arithmetic and logical operations. Among its core elements, the multiplier holds particular significance, finding widespread use across various digital applications, notably in scientific computing and Digital Signal Processing. The pursuit of enhanced system performance necessitates the integration of a high-performance multiplier. The efficacy of the adder directly impacts the multiplier's efficiency. Since most of the time spent by a multiplier is on adding partial products, leading to considerable delays. This study offers a comprehensive evaluation of five commonly utilized adders-Ripple Carry Adder (RCA), Carry Save Adder (CSA), Carry Look-Ahead Adder (CLA), Carry Select Adder (CSLA), and Carry Skip Adder (CSKA)-across a 4-bit length to ascertain the most effective adder. The identified high-performance adder was subsequently employed in the design of three distinct 32-bit multipliers: Array, Booth, and Vedic. Utilizing the Verilog Hardware Description Language (HDL) for modeling, both adder and multiplier were simulated using Quartus Prime Lite. Performance comparison revolved around three key parameters: area, delay, and power consumption. Among the adders evaluated, the CLA adder exhibited approximately 15% less delay, alongside lower area and power consumption (1800 μm2, 330 mW respectively) compared to its counterparts. Integration of the high-performance CLA adder into the Array multiplier showcased superior performance, evidenced by a significant reduction of approximately 50% in both area and delay, coupled with a notable 3.1% decrease in power dissipation compared to multipliers without CLA integration.