Performance Assessment of 3D Network-on-Chip Architecture using Ensemble Learning Technique
Ramapati Patra, Hemanta Kumar Mondal · 2024
For System-on-Chip (SoC) designs, Network-on-Chip (NoC) provides a scalable and promising interconnect solution that is particularly well-suited for high-performance computing platforms. Within SoC designs, the 3D Network-on-Chip (3D NoC) architecture further improves communication efficiency. Throughput, latency, and overall energy consumption are important factors that affect how well 3D NoCs perform overall. Nevertheless, using a cycle-accurate simulator to simulate these systems requires a significant execution time for varying packet injection rate values. To predict crucial parameters for 3D NoC designs, this work presents a stacking ensemble regression techniques involving combining multiple machine-learning models like Linear regression (LR), Support vector regression (SVR), Decision tree regression (DTR), K-nearest neighbour (KNN), and Polynomial regression (PR) models to improve predictive performance and robustness. The obtained results are compared with the cycle-accurate simulator for NoCs. The experimental results showed an R2 score and RMSE up to 0.9922 and 0.0049, and MAE and MAPE up to 0.0034 and 0.0482. Moreover, the proposed regression model achieves a maximum speedup of approximately 5995.3X compared to a cycle-accurate simulator. This work outperforms existing works regarding speedup, MAE, and RMSE.