General-Purpose Quantum Circuit Generator for Partially Fault-Tolerant Quantum Computing Architecture
Yutaro Akahoshi, Jun Fujisaki, Hirotaka Oshima, Shintaro Sato, Keisuke Fujii · 2024
Quantum computers hold the promise of revolutionizing several computational tasks by significantly enhancing their calculation speed compared to classical computers. However, there is still a large gap towards fault-tolerant quantum computing (FTQC) due to the large requirement of physical qubits. Under these circumstances, authors proposed a partially fault-tolerant quantum computing architecture that consists of the fault-tolerant Clifford gates and the sufficiently clean analog rotation gate, named “Space-Time efficient Analog Rotation gate quantum computing architecture (STAR architecture).” Although its theoretical foundation is given, we need to develop an efficient software implementation tailored for STAR architecture due to its unique choice of the fundamental gate set. In this study, we construct an integrated software system of STAR-architecture-based quantum computation, which generates physical instructions executable on quantum devices from input logical quantum circuits. The system mainly consists of two parts, a circuit converter and an operation controller. The circuit converter comprises a set of conversion subroutines, which bridge several instruction layers: logical circuit layer, lattice surgery layer, and physical circuit layer. The operation controller efficiently executes the generated instructions. Especially, it enables efficient treatment of the analog rotation gate, which needs real-time scheduling of running instructions due to its probabilistic nature.