A Power Reduction Scheme by Arithmetic Format Conversion for a DSP to Estimate Qubit States Under 4K Cryogenic Environment
Takashi Imagawa, Ryo Kishida, Yuki Koyama, Kazutoshi Kobayashi, Takefumi Miyoshi · 2024
In order to deploy quantum computer systems into various fields, the number of qubits in a quantum computer unit must be increased by a very large factor. One of the factors that disrupt the increase is the large scale of the quantum-classical interface (QC-IF) in a room temperature environment. We aim to reduce the scale of the control infrastructure by implementing a digital signal processor (DSP) that can operate at cryogenic environments. The DSP reduces the communication rate by encoding and decoding the signals exchanged between the qubits and the QC-IF, thus reducing the scale of the infrastructure. This DSP is required to have low power consumption so as not to disrupt the cryogenic environment by its own heat dissipation. This poster focuses on a DSP for estimating the state of qubits. In the existing implementation, the large internal memory (SRAM) dominates its power consumption and circuit area. In this poster, we convert the arithmetic data format in a sub module containing the large SRAMs from extra-long integers to single-precision floating-point numbers. This modification reduces the power and area of the entire circuit by 47.7% and 54.3%, respectively. We confirmed that this modification does not affect the processing performance and the primary output value.