Hardware Attack Models in Tiled Chip Multi-Core Processors: A Survey
Nilanjana Das, Friedrich Pauls, Mattis Hasler, Sebastian Haas, Nils Asmussen · 2024
An increasing number of use of third-party IP participation along with the growing need for sophisticated Tiled Chip Multi-Core Processor systems (TCMP) led to vulnerability exploitation in the integrated circuit (IC) supply chain, primarily the insertion of hardware Trojans (HTs). The HTs are malevolent alterations made to genuine designs to compromise IC performance. In this study, we first evaluate the most recent HT attack models in TCMPs, emphasizing the targeted platform, the supply chain’s risk level, and then a discussion based on our findings. We classify the HT attack models according to the targeted platforms in TCMP, like processor, caches, network interface, router, and virtual channel allocator.