Two-level Routerless Network-on-Chip
Fawaz Alazemi, Ahmed Humoud · 2024
Chip MultiProcessor (CMP) designs are rapidly advancing to meet the growing demand for computational power driven by applications in artificial intelligence, scientific computing, and big data analytics. A crucial component of these designs is the Network-on-Chip (NoC) which facilitates communication between components (cores, memory, etc) on a chip. Traditional NoCs rely on on-chip routers for communication but these introduce significant power and area overheads which limits its scalability to accomodate high number of cores. The Routerless NoC (RLNoC) offers an alternative by eliminating routers and forming cheap and simple disjoint communication loops between cores. Thus, reducing power consumption and area requirements. However, RLNoC’s scalability is constrained by its flat design and limited path diversity. In this paper, we introduce a two-level Routerless NoC (2RLNoC), which divides the network into islands interconnected by horizontal and vertical loops where flits are allowed to switch from a horizantal loop to a vertical loop only once for more a better path diversity. Simulation results show that 2RLNoC achieves up to 8.63x better path diversity and up to 2.46x higher throughput compared to RLNoC. These results highlight the potential of 2RLNoC as an effective solution for improving the scalability and performance of future routerless-based CMP designs.