Hator: A High-Efficiency CGRA-Based 32/64-Bit Hashing Accelerator with Real-Time Performance Analysis
Hai Hau Nguyen, Pham Hoai Luan, Vu Tuan Hai, Van Duy Tran, Vu Trung Duong Le, Duc Khai Lam, Thi Diem Tran, Yasuhiko Nakashima · 2024
Developing hashing hardware to support diverse 32-bit and 64-bit hash functions at high speed and with low power consumption is necessary to meet the varied security requirements in the rapid explosion of blockchain and IoT integration. Over the past decade, a coarse-grained reconfigurable array (CGRA) has emerged as the most efficient hardware architecture to facilitate high flexibility, high performance, and low power for cryptography. However, existing CGRA-based cryptographic accelerators currently support only 32-bit hash functions and lack real-time performance evaluation on actual hardware. To address these issues, this paper proposes a CGRA-based hashing accelerator named Hator to support a variety of 32-bit and 64-bit hash functions with high speed and energy efficiency on actual FPGA hardware. Three new ideas are proposed to achieve these goals, including the Processing Element Array eXtension (PEAX), which allows data processing with up to 64-bit granularity; a dual Arithmetic Logic Unit (ALU) to maximize hardware resources for both 32-bit and 64-bit operations; and a massive data processing mechanism with multiple pipelined working sessions for efficient calculating of large amounts of continuous data. Accordingly, the real-time performance analysis of Hator on various hash functions shows that the power-delay product (PDP) of the Hator is better than that of powerful CPUs by 8.08-42.49 times. Additionally, evaluations on ASICs with 45nm CMOS technology show that the Hator outperforms existing CGRAs by 1.77 to 3.49 times in throughput and 1.37 to 20.42 times in energy efficiency.