SPARKLE: 400 RISC-V GIPS with 1,024 Barrel Processors on a single Datacenter FPGA Card
Riadh Ben Abdelhamid, Vladislav Válek, Dirk Koch · 2024
SPARKLE is a many-core multi-threaded RISC-V architecture designed for scalable parallel processing. Our implementation on a Xilinx VU9P datacenter-class FPGA comprises 1,024 cores, and 16,384 Harts (Hardware threads), clocking at 400MHz and spanning the entirety of the chip, including a PCIe backplane. As such, SPARKLE delivers 400 GIPS (Giga Instructions Per Second), demonstrating the feasibility of large-scale high-speed parallelism. SPARKLE is very flexible and allows users to define different configurations for memory, instruction set extensions, and cluster organizations. For instance, a smaller-footprint 56-core (896-Hart) cluster can operate at 500 MHz, on the same chip.At the heart of SPARKLE, its core, code-named BRISKI (Barrel RISC-V for Kilo-core Implementations) is among the fastest existing on literature and can operate at 650+ MHz. BRISKI is a highly-optimized barrel processor core that implements the full user-mode RV32I, as well as RV32A LR.W/SC.W subset and CSRRS instruction for Hart ID retrieval.