Pseudo-Sim: An Accurate Analytical Modeling Framework for Systolic Array Architectures
Dan Sturm, Sajjad Moazeni · 2024
Array-based accelerators have emerged as powerful compute engines for meeting the immense computational de-mands of artificial intelligence (AI). However, current tools for optimizing their complex multidimensional hardware-software design space feature a strict tradeoff between accuracy and runtime. Here, we introduce Pseudo-Sim, a rapid and accurate methodology to simulate key system parameters including the number of compute clock cycles, off-chip DRAM accesses, and SRAM accesses. We validate the effectiveness of our tool by running it on the Resnet50V1.5 and BERT-Base neural networks for multiple hardware configurations and comparing results to those from a a cycle-accurate simulator. Pseudo-Sim achieves$10^{4}\times$speedup).