Advanced Verification Strategies for Memory Block Integration in Processor Design
N. U. Bhuvana Gowda, Eleena Mohapatra · 2024
This paper introduces a versatile verification architecture designed for Non-Volatile Memory (NVM) blocks with varying data widths-32-bit, 64-bit, 256-bit, and 512-bit. The proposed approach employs the Universal Verification Methodology (UVM) to systematically verify these memory blocks, both at the block level individually and at the top level collectively using multiplexing logic. The verification framework leverages the commonalities among the different memory blocks, allowing for the creation of customizable scoreboards, sequences, stimuli, UVM components, payloads, and test scenarios. Importantly, this UVM flow is not tailored to any specific memory block but is developed in a generalized manner, making it applicable across various memory configurations. By reducing the dependence on extensive macros, methods, and classes, this architecture simplifies the verification process while ensuring high reusability and flexibility, ultimately making it effective for a wide range of memory verification task