An 8T Single Bit-Line Content Addressable Memory Cell for High-Performance Searching Applications
Arnav Banerjee, Sheikh Wasmir Hussain · 2024
Content addressable memory (CAM) is essential for applications that demand rapid search capabilities. Its ability to perform high-speed search within a single clock cycle requires CAM cell to incorporate an additional comparison unit, which contributes approximately 30%- 40% more transistors than storage unit. As a result, the CAM arrays occupy more space than traditional memory systems such as static random access memory (SRAM), and the enhanced performance comes at a significant increase in power consumption. We propose a CAM cell design that utilizes one of the access transistors as a half-side comparator, allowing for a single bit-line (BL) configuration instead of complementary BLs. This innovative approach not only decreases the number of transistors and the memory core area but also cuts down half of the BL switching activities, leading to a more efficient CAM design. Based on 180-nm 1.8-V CMOS technology, our 64×32-bit CAM utilizing the single bit-line CAM cell (SBCC) achieves 59% better energy-delay performance compared to a conventional design and 10% better than a previous full swing cell based CAM design, while using 1.25 × fewer transistors.