Efficient Pipelined Hardware Architecture for Depth-Map-Based Image Dehazing System
K. Vidyamol, Matcha Surya Prakash, Praveen Sankaran · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2024
Hazy images can be made clear with the image dehazing process. Advanced driver-assistance systems (ADASs) may have a preexisting stage to maintain clear driving visuals in foggy situations. ADAS strives for greater image resolution at a faster frame rate in order to maintain its dependability for road safety. This tendency forces image dehazing to contend with a formidable throughput challenge with improved power constraints. This work proposes a hardware-efficient, computationally light image dehazing engine. It consists of two main techniques: the saturation-based local airlight estimation module (SLAEM) and the depth-map transmission-map estimation unit (DMTMEU). The transmission-map estimation task and the airlight estimate task can be executed concurrently due to the adopted depth map-based transmission estimation approach, eliminating the dependence between the two activities. In terms of pixels, an additional advantage of the adaptive airlight estimation approach is that it avoids the computationally demanding sorting step, which helps to increase hardware efficiency. The entire architecture utilizes look-up table (LUT)-based computations to implement division modules and exponential functions, resulting in more optimized architecture than the existing dehazing architectures. The Taiwan Semiconductor Manufacturing Company (TSMC) CMOS 90-nm technology is used in the implementation of this study. It is arranged into a six-stage pipelining approach to create a seamless data scheduling process. It achieves a throughput of 200 Mp/s with a logic gate count of 9.309 K and a power consumption of 2.61 mW at 200 MHz. The experimental results demonstrate a 20.09% reduction in area and a 31.31% reduction in power compared to best-performed existing systems, highlighting significant performance improvement.