Efficient RTL design of an ALU utilizing hybrid adder logic
Subham Das, Debasis Mondal, Shreya Adhikary · 2024
According to Moore’s law, the number of transistors in an integrated chip will grow exponentially over time, leading to increased design complexity. This rising complexity, driven by the demand for high-speed multitasking processors, has reached a point where power consumption and interconnect delays are major concerns for chip designers. To address these physical limitations in VLSI design, various methodologies have been developed. One such approach involves designing at the register transfer level (RTL) platform. In this methodology, the chip is initially designed using a hardware description language (HDL) to determine the RTL. This paper presents an optimized RTL design for an 8-bit Arithmetic Logic Unit (ALU). The proposed design was simulated using a SpartanTM-3 family FPGA with Xilinx ISE 14.7. The key innovation in this model is an RTL-optimized adder unit. Given that the performance of any ALU heavily relies on the efficiency of its adder unit, designing an RTL-optimized adder has been a significant area of research for several decades. Recently, hybrid logic has been employed to minimize adder delay. Our proposed design introduces a new hybrid full adder (FA) design. Detailed analysis reveals that the carry select adder, utilizing hybrid logic in the FA block, demonstrates superior performance compared to existing ALU designs.