Development of Low Power GNSS correlator in Zynq SoC for GPS and GLONSS
Journal of VLSI Circuits and Systems Β· 2024
This paper presents the design of a comparator with low power, low offset voltage, high resolution, and rapid speed.The designed comparator is built on 45 ππππ flip CMOS technology and runs 4.2 πΊπΊ samples per second at nominal voltage.It is a custom-made comparator for a highly linear 4-bit Flash A/D Converter (ADC).The outlined design can operate on a nominal supply of 1.8 V.The comparator offset voltage was elevated because of this mismatch.To compensate for the offset voltage, we followed a decent approach to design the circuits.Therefore, the offset voltage is reduced to 250ππππ.The designed comparator has a unity gain bandwidth of 4.2 πΊπΊπΊπΊπΊπΊ and a gain of 72ππππ at nominal PVT, which gives us a considerable measure of authority.The dynamic power consumption of the comparator is 48.7ππππ.The layout of this designed comparator has been implemented, and the area of the comparator is 12.3 ππππ Γ 15.75 ππππ.The results of pre-and post-layout simulations in various process, voltage, and temperature corners are shown.