Implementation of Full Adder Logic using XOR-XNORLogic
K Vanitha, K. Lokesh Krishna, Hariprasad Tarigonda, Sunkesula Chanu · 2024
Advances in Complementary Metal Oxide Semiconductor (CMOS) scaling techniques have led to the proliferate usage of multimedia devices such as laptops, mobiles, graphic cards, personal digital assistants etc. In all these applications, the low power, low die size and high speed fundamental adder architectures are essential. Various algorithms such as fast-fourier, discrete cosine transforms and inverse discrete cosine transform are used. To implement these algorithms, adders with enhanced performance features such as low area and high speed computation are vital and necessary. Several adder architectures are available for different applications. In this paper, a ten transistor using CMOS Exclusive OR and Exclusive NOR gates in combination is proposed. The full adder logic circuit is designed and simulated in cadence virtuoso too environment and operated a dc voltage of 1.5 V in 0.09 micrometer process technology. The proposed ten transistor full adder logic circuit on an average operates at 14 percent less power when compared to the conventional CMOS logic full adder circuit. The propagation delay performance was also slightly better when compared to previous circuit. Both the full adder logic simulations have been carried for multiple dc voltages and performance analysis (i.e. power delay product) has been carried out at the end of the paper.