SubMap: A Partial Mapping Strategy for CGRA Based on sub-CGRA Exploration
Ning Li, Dejian Li, Zhipeng Wu, Peiguang Jing, Sio Hang Pun, Yu Liu · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2024
Coarse-grained reconfigurable array (CGRA) is a quality hardware for compute-intensive loop kernels, with its excellent balance of performance, energy efficiency, and reconfigurability. However, the efficiency of CGRA depends heavily on how the compiler maps the data flow graph (DFG) extracted from application kernels onto the target architecture. Most existing CGRA compilers encounter the challenge of long compilation times due to excessive exploration space. To reduce the exploration space and compilation time, we propose SubMap, which adaptively explores a suitable sub-CGRA for different DFGs in a target CGRA and efficiently performs the mapping process. The experimental results show that SubMap greatly reduces the compilation time compared to the latest methods while maintaining the mapping quality. On HyCube$4\times 4$, SubMap has an average performance improvement of$9.47 \times $and$11.67 \times $, respectively, compared with Morpher (Pathfinder) and Morpher (SA). As the scale of the target CGRA increases, the performance improvement of SubMap becomes more pronounced.