An energy-efficient adaptive two stage pipeline RISC-V based soft-processor for edge-computing applications
S. Kumar, Kailash Chandra Ray · International Journal of Parallel Emergent and Distributed Systems · 2024
This paper introduces a highly adaptable RV32I soft-processor architecture tailored for energy-restricted edge computing. Notably, it features a adptive two-stage pipeline with dynamic control to optimise energy consumption, activating the second stage selectively during memory operations. Implemented in Verilog HDL and validated on an FPGA platform, the architecture achieves impressive energy efficiency at 0.54 mW/M Hz. Comparative experiments demonstrate a substantial 28.2% reduction in average power usage compared to state-of-the-art single-cycle RV32I processors. These advancements position the design as highly suitable for energy-constrained edge computing applications, addressing critical efficiency challenges in resource-limited environments.