Floating Point Multiplier using High Performance Adders and Multipliers
Mr. Chethan B R, T S Samarth, T. Praveen, V Vishwas, S D Mruthyunjaya · INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT · 2024
This paper presents a high-performance floating- point multiplier designed using advanced adder and multiplier architectures to enhance computational efficiency and speed for FPGA-based applications. The design employs Carry Bypass Adder (CBA) and Kogge-Stone Adder (KSA) to optimize partial product accumulation, along with Wallace Tree and Systolic Multiplier architectures for efficient parallel multiplication. Implemented in compliance with the IEEE 754 single-precision floating-point standard, the proposed multiplier is synthesized and simulated using the Vivado design suite. Comprehensive analysis highlights the trade-offs between the architectures in terms of latency, power consumption, and resource utilization. The results demonstrate significant improvements in performance, making this design ideal for high-speed applications such as signal processing and machine learning. Key Words: IEEE 754, FPGA, High-Speed Computation, Low Latency, Resource Optimization.