Exploring the Role of the Portable Stimulus Standard in Enhancing Security Property Verification
Jaimini Nagar, Thorsten Dworzak, Sebastian Simon, Ulrich Heinkel, Djones Vinicius Lettnin · 2024
The security of the hardware design has been a critical concern in the semiconductor industry in the recent years. Modern integrated circuit designs of the security-critical application contain numerous sensitive data that needs to be protected against adversary attacks. An Intellectual Property (IP) block such as security controllers is integrated into the System on Chip (SoC) to protect the sensitive asset and its integrity with certain measures that implement cryptographic algorithms. Verification of security properties of this type of IP block is especially important and crucial to ensure its trustworthiness. This paper presents an approach to enhance security property verification of the design using Portable Test and Stimulus Standard (PSS) along with existing testbench. PSS defines a specification to generate a single representation of stimulus and test scenarios, which is usable by a various user across different level of integration. We have modelled functionality and security property of the Security Controller IP at abstract level using PSS. Then, PSS model has facilitated to generate a set of concrete test cases in Specman/e for various scenarios. The generated test cases are executed in verification environment and analyzed the results that verify security properties.