Optimization design for low-density parity-check codes in NAND flash memory systems
Zhou Xuan, Zheng Ma, Qike Pang, Xiaohu Tang · Scientia Sinica Informationis · 2024
The escalating demand for high-capacity storage has spurred significant advancements in NAND flash memory technology. However, this quest for increased storage density has inadvertently compromised the resilience of NAND flash memory systems to interference. Consequently, the optimization of error control code designs for NAND flash systems has emerged as a pivotal area of research.In this study, we initiate a comprehensive analysis of interference phenomena within NAND flash memory systems. Due to the asymmetric and non-Gaussian nature of the threshold voltage across memory cells, we have opted for a modified Student's t-distribution to better model these characteristics.Subsequently, we employ a discrete asymmetric density evolution (DE) algorithm to analyze the effects of quantization on low-density parity-check (LDPC) codes.We then harness a differential evolution algorithm to optimize the parameters of the irregular LDPC codes.Finally, we optimize the codebook in the IEEE standard of flash memory.Simulation results show that our optimized codebook enhances error correction performance by an order of magnitude.Furthermore, the optimized codebook significantly prolongs the operational lifespan of memory cells.