A 360 GOPS/W CGRA in a RISC-V SoC with Multi-Hop Routers and Idle-State Instructions for Edge Computing Applications
Vishnu P. Nambiar, Yi Sheng Chong, Thilini Kaushalya Bandara, Dhananjaya Wijerathne, Z. Li, Rohan Juneja, Li-Shiuan Peh, Tulika Mitra, A. T. Do · 2024
Although custom designs for AI/ML workloads on resource-constrained devices are capable of high energy efficiency, they are usually tailored for a single task or a narrow range of applications. Coarse-grained reconfigurable arrays (CGRAs) can bridge this gap by using software-defined computing engine to offer both energy efficiency and flexibility across wide range of workloads. This work presents a versatile CGRA design with 17 integer and logic instructions, multi-hop data transfers and hardware customized idle-state power saving op-code. The proposed CGRA was fabricated in the 40nm technology node and delivers a peak efficiency of 360 GOPS/W, which is 1.2× to 4.6× higher than the state-of-the-art.