Efficient Built-In Self-Test Scheme for Inter-Die Interconnects of Chiplet-Based Chips
Yi‐Chun Huang, Pei-Yun Lin, Jin-Fu Li, Hong-Siang Fu, Yung-Ping Lee · 2024
Various advanced packaging technologies have been proposed to integrate multiple dies into a package. In the multidie package, a significant amount of inter-die interconnects are used to assemble the dies. The bonding interfaces, e.g., microbumps (ubumps), of the inter-die interconnects are prone to defects during the assembly process. Therefore, it is crucial to test the inter-die interconnects to ensure the quality of the assembly. In this paper, we propose an efficient built-in self-test (BIST) scheme for the testing of inter-die interconnects of chiplet-based ICs. The transmitters/receivers under test are logically arranged as a 2D array. A test algorithm that utilizes alternating row stripe and column stripe test patterns is proposed. These 2D test patterns are then compressed into 1D test patterns such that the test application time can be reduced. Simulation and analysis results show that the proposed BIST scheme can achieve 99.9% test time reduction and save about 53.5% area cost for a 32×64 ubump array in comparison with a typical test scheme, IEEE 1500 test scheme.