An Effective TMR Approach for Low-Latency Configurable-Accuracy Adders
Ioannis Tsounis, Dimitris Agiakatsikas, Mihalis Psarakis · 2024
Low-Latency Approximate Adder (LLAA) is a high-performance type of approximate adder, which can still produce an exact output by integrating proper Approximation Error Detection and Correction (AxEDC) extra circuitry for detecting and correcting the expected approximation error. Furthermore, the hardware accelerators may be used for applications susceptible to hardware (HW) faults, which can produce additional errors to the adders during their lifetime. We propose an effective TMR methodology which exploits the resemblance of the errors caused by HW faults with the approximation errors both either case of AxEDC integration or not. We modify the AxEDC unit to detect and correct both types of errors and triplicate selectively parts of the adder. Our methodology achieves to minimise significantly the area overhead while also increasing the performance gain.