Design and Analysis of Self Testable Fast Multiplier Architecture
Abhay Goyal, Sreeja Rajendran · 2024
Multiplication operations play a fundamental role in numerous digital applications, and guaranteeing their accuracy is imperative for reliable system performance. The research carried out in this paper entails two primary aspects. Initially, an 8x8 unsigned fast multiplier is developed which is a modified Wallace tree multiplier. The choice of employing a Wallace tree multiplier is motivated by its ability to minimize latency. Additionally, to further boost the speed of the Wallace tree multiplier, a Kogge Stone adder module is incorporated. Further, a Built-In Self -Test (BIST) module is designed for the modified Wallace tree multiplier. The efficacy of the BIST is evaluated by considering Stuck at fault model, ensuring thorough test coverage. The BIST mechanism is customized to identify stuck-at faults within the multiplier module.